Method for fabricating a layer arrangement, layer arrangement and memory arrangement

ABSTRACT

The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a substrate and at least one respectively laterally defined second layer sequence is embodied on a second surface area of the substrate in order to produce a layer arrangement. A first side wall having a first thickness is respectively produced from a first electrically insulating material on at least one partial area of the side walls of the first and second layer sequences. A second side wall layer having a second thickness is respectively produced from a second electrically insulating material on at least one partial area of the first side wall layers and the second side wall layers are removed from the first layer sequences.

REFERENCE TO RELATED APPLICATIONS

This application is related to and claims the benefit of priority under35 U.S.C. §§120, 271 and 365 to Patent Cooperation Treaty patentapplication no. PCT/DE2003/001581, filed on May 15, 2003, which waspublished at WO 2003/098694, in German.

This application is further related to and claims benefit of priorityunder 35 U.S.C. §119 to the filing date of May 16, 2002 of German patentapplication no. 10221884.6 DE, filed on May 16, 2002.

FIELD OF THE INVENTION

The invention relates to a method for fabricating a layer arrangement,to a layer arrangement and to a memory arrangement.

BACKGROUND

In view of the rapid ongoing development of computer technology, thereis a need for a memory medium which makes it possible to store an evergreater quantity of information on ever smaller arrangements. In thefield of non-volatile memories, which, once they have been programmedwith the information item to be stored, retain this information itempermanently without ever losing it, it is customary for data quantitiesof one bit or more to be stored in each transistor of a largearrangement of transistors. By way of example, Widmann, D, Mader, H,Friedrich, H (1996) “Technologie hochintegrierter Schaltungen”[Large-scale integrated circuit technology], Chapter 8.4, SpringerVerlag, Berlin, ISBN 3-540-59357-8, provides a summary of non-volatilememories.

As miniaturization continues, conventional silicon microelectronics willreach its limits. In particular, the development of ever smaller andmore densely arranged transistors, which has by now reached severalhundred millions of transistors per chip, will come up against basicphysical problems in the next ten years. When feature sizes drop below80 nm, the components are disruptively affected by quantum effects, andthese effects become dominant at sizes of below approximately 30 nm.Also, the increasing integration density of the components on a chipleads to a dramatic rise in the waste heat which is generated.Therefore, increasing the storage density of transistor arrangements bymeans of ongoing miniaturization of the structure dimensions is aconcept which imposes high technological demands on the basicfabrication methods.

In the case of what is known as embedded technology, transistors withdifferent requirements are integrated in a single integrated circuit,i.e. in a chip. For example, it may be necessary to integratetransistors of different configurations in a memory region of the chip(for example in a flash memory arrangement or an EEPROM) and in a logicregion of the integrated circuit. In a scenario of this nature,different demands are imposed on the structural and physical parametersof the integrated transistors.

To form a transistor in a logic region, which logic region is to besufficiently fast, a logic transistor of this type needs to be separatedfrom its surroundings by a side wall oxide layer which is as thin aspossible. A thin side wall oxide layer is necessary in a logictransistor in order to ensure a low connection resistance: a layerarrangement which serves as a logic transistor on a substrate can becoupled to the surroundings by doping atoms being injected into theboundary regions on both sides between the laterally delimited layerarrangement and the substrate (“lightly doped drain”). If in the case ofa logic transistor, the side wall oxide layer is too thick, the regionof overlap between the doped region in the silicon substrate and thegate oxide region of the transistor is small, and consequently the logictransistor has a high impedance. In other words, the further the lightlydoped drain regions are formed outside the end sections of the logictransistor on both sides, the higher the impedance of the logictransistor becomes. To ensure that the logic transistor is sufficientlyfast, the side wall oxide layer of the logic transistor should thereforebe sufficiently thin (e.g. approx. 5 nm to 7 nm for the 130 nmtechnology generation). On the other hand, it is important for a sidewall oxide layer to be present in a logic region, in order to form awell-defined surface at the side wall of the gate electrode made frompolysilicon (polycrystalline silicon), in order to saturate surfacecharges as occur, for example, during the method of fabricating thelogic transistor and to anneal plasma etching damage as may occur, forexample, during the CVD (chemical vapor deposition) process which isfrequently used in the fabrication of transistors.

On the other hand, it is aimed for the side wall oxide layer of a memorytransistor in a flash memory or an EEPROM memory to be a sufficientlythick side wall oxide layer. A sufficiently thick side wall oxide layerensures in a charge-storage layer that the information which is storedin the memory transistor and is coded in the amount of electric chargecontained in the charge-storage layer is reliably retained. This leadsto a sufficiently long hold time for the stored information, which isessential for the functionality of a memory transistor. Furthermore, athick side wall oxide layer in a memory transistor leads to theavoidance of ion damage at the tunnel oxide edge, which adverselyaffects the functionality of a memory transistor, and to the avoidanceof undesirable charging of the floating gate by subsequent implantationsof ions for forming doped regions in surface regions of a substrate.Furthermore, a sufficiently thick side wall oxide layer keeps boundarycharges caused by a silicon nitride spacer which is often formed duringfabrication of the memory transistor away from the floating gate or fromthe gate oxide layer, thus ensuring perfect functionality of the memorytransistor. The thickness of the side wall oxide in a memory transistorshould be at least 10 nm.

The contradictory demands imposed on the thicknesses of the side walloxide layers in a logic transistor and in a memory transistor on a chipwhich has both a logic region with rapid integrated logic for drivingthe memory region and a memory region with a multiplicity of memorytransistors are often only taken into account in the prior art to theextent that a uniform thickness is selected for the side wall oxidelayers of the logic transistors and the memory transistors. This uniformthickness is selected to be sufficiently small to obtain a logictransistor with a side wall thickness which is reasonably acceptable inthe logic region and is also selected to be sufficiently great to obtaina memory transistor with a reasonably acceptable side wall thickness inthe memory region. However, this compromise solution adversely affectsthe functionality of both types of transistors for the reasons listedabove.

A compromise solution of this type is increasingly unsuitable fortechnologies which deal with transistors with a gate region length of130 nm and below, if perfect functionality of the integrated circuitswhich these technologies produce is to be ensured. For a transistor witha gate region length of 130 nm and below, a side wall oxide thickness ofsignificantly less than 10 nm is required for a perfectly functioning,sufficiently fast logic transistor, but this thickness is much too lowfor a memory transistor in a flash memory or an EEPROM.

The prior art has disclosed a method which makes it possible tofabricate an integrated circuit having a logic region with a logictransistor and a memory region with a memory transistor integrated on acommon chip and in which the side wall oxide of the logic transistor andof the memory transistor can be formed in different thicknesses.

A method of this type, which involves the formation of logic transistorswith a side wall oxide which is thinner than the side wall oxide ofmemory transistors formed on the same integrated circuit is describedbelow with reference to FIGS. 1A-1I.

In the abovementioned figures, a left-hand region of the layerstructures shown in each case represents a logic region of an integratedcircuit (or more specifically a logic transistor of the logic region),and the region shown on the right-hand side represents a memory region(or more specifically a memory transistor of the memory region) of theintegrated circuit. This is visually indicated in FIGS. 1A-1I by thefact that a dashed vertical line is included in the drawing, separatingthe logic region formed to the left of the dashed line from the memoryregion shown to the right of the dashed line.

To arrive at the layer structure 100 shown in FIG. 1A, a first silicondioxide layer 102, a first polysilicon layer 103 and an ONO layersequence 104 are deposited on a silicon substrate 101. An ONO layersequence is a three-layer sequence comprising in each case one layer ofsilicon dioxide, silicon nitride and silicon dioxide. The first of thesilicon dioxide layers of the ONO layer sequence 104 is deposited on thefirst polysilicon layer 103, the silicon nitride layer of the ONO layersequence 104 is deposited on the first silicon dioxide layer of the ONOlayer sequence 104, and the second silicon dioxide layer of the ONOlayer sequence 104 is deposited on the silicon nitride layer of the ONOlayer sequence 104.

The layer structure 105 shown in FIG. 1B is obtained by removing thefirst silicon dioxide layer 102, the first polysilicon layer 103 and theONO layer sequence 104 from the entire logic region using a lithographyprocess and an etching process.

To convert the layer structure 105 shown in FIG. 1B into the layerstructure 106 shown in FIG. 1C, a second silicon dioxide layer 107, asecond polysilicon layer 108 and a suitable hard mask 109 are depositedover the entire surface of the layer structure 105.

The layer structure 110 shown in FIG. 1D is obtained by the layerstructure being patterned in the memory region (i.e. in the region tothe right of the dashed line in FIG. 1C, FIG. 1D), whereas the logicregion (region to the left of the dashed line in FIG. 1C, FIG. 1D) iscovered. Since the structures formed in the memory region must liewithin a small structural tolerance range, this patterning step is ofcrucial importance. This means that even slight inaccuracies in thismethod step will have a considerable influence on the functionality ofthe integrated circuit fabricated in this way. Therefore, this methodstep requires accurate setting of the process conditions, making thismethod step complex and expensive. As shown in FIG. 1D, only the topfive layers are patterned in the memory region, whereas the firstsilicon dioxide layer 102 is retained in the memory region as well. Thiscan be achieved by using a suitable etching process which is set up insuch a manner that the etching process stops before the first silicondioxide layer 102.

To achieve the layer structure 111 shown in FIG. 1E, the laterallydelimited layer sequence which remains in the memory region after thepatterning is covered with a first side wall oxide layer 112. This sidewall oxide initially also grows on surface regions other than thelaterally delimited layer sequence, including over the layers 102 and109, and can be etched back, resulting in the layer sequence 111 shownin FIG. 1E. This leads to only a slight raising of the hard mask layer109 (not shown) in the entire logic region during this method step. Inother words, the side wall of the laterally delimited layer sequence inthe memory region is covered with the first side wall oxide layer 112,whereas the logic region remains virtually unchanged.

The layer structure 113 shown in FIG. 1F is obtained by keeping thelogic region covered while doping atoms are introduced into thosesurface regions of the silicon substrate 101 which are not covered bythe laterally delimited layer sequence, using an ion implantationmethod, with the result that the LDD (lightly doped drain) regions 114a, 114 b are formed.

To achieve the layer structure 115 shown in FIG. 1G, the memory regionis then completely covered and the logic region is patterned using alithography process and an etching process. To pattern the logic regioninto a laterally delimited layer sequence, a further patterning step ofcrucial importance is required. This means that even slight fluctuationsin the procedure will immediately have an adverse effect on thefunctionality of the logic regions formed in this way. As with the firstcritical patterning step described above, this method step too requiresa complex and expensive procedure which needs to be highly accurate. Asshown in FIG. 1G, only the top two layers, namely the second polysiliconlayer 108 and the hard mask 109, are patterned, whereas the secondsilicon dioxide layer 107 is not removed from the surface of the layerstructure arranged in the logic region as a result of a suitable etchingprocess being used. Consequently, the laterally delimited layer sequencewhich is shown in FIG. 1G and comprises the second polysilicon layer 108and the hard mask 109 remains in place on the logic region.

The layer structure 116 shown in FIG. 1H is obtained by in each caseapplying a second side wall oxide layer 117 to the laterally delimitedlayer sequences in both the logic region and in the memory region of theflash memory or EEPROM. This is achieved by thermal oxidation of theside walls. The second side wall oxide layer 117 has a lower thicknessthan the first side wall oxide layer 112. As shown in FIG. 1H, thelaterally delimited layer sequence in the logic region thereforeincludes a side wall oxide which corresponds to the thickness of thesecond side wall oxide layer 117, whereas the laterally delimited layersequence in the memory region includes a side wall oxide layer whosethickness is composed of the thickness of the first side wall oxidelayer 112 and the thickness of the second side wall oxide layer 117.

To achieve the layer structure 118 shown in FIG. 1I, implantation stepsare carried out in both the logic region and the memory region, with theresult that the first doped region 119 a and the second doped region 119b are obtained in the logic region. In this way, the first HDD region120 a and the second HDD region 120 b are produced in the memory regionat the end sections of the laterally delimited layer sequences on bothsides. HDD means highly doped drain, expressing the fact that theconcentration of doping atoms in the HDD regions 120 a, 120 b is greaterthan in the LDD regions 114 a, 114 b. The laterally delimited layersequence formed in the logic region forms a transistor with a side walloxide having the thickness of the second side wall oxide layer 117. Thefirst doped region 119 a represents the first source/drain region,whereas the second doped region 119 b forms the second source/drainregion. The second silicon oxide layer 107 in the logic region forms thegate oxide layer, and the second polysilicon layer 108 forms the gateelectrode in the logic region. The second side wall oxide layer 117 isused to laterally shield the transistor, and the hard mask 109 islikewise used as a protective layer.

The laterally delimited layer sequence formed in the memory region canbe used as a memory transistor. The first LDD region 114 a and the firstHDD region 120 a form the first source/drain region, the second LDDregion 114 b and the second HDD region 120 b form the secondsource/drain region. The first silicon dioxide layer 102 constitutes thegate oxide region. The first polysilicon layer 103 can fulfill thefunctionality of a floating gate into which charge carriers can bepermanently injected, for example by means of Fowler-Nordheim tunnelingor by means of hot electrons. The ONO layer sequence 104 and the secondsilicon dioxide layer 107 effect electrical decoupling of the floatinggate from the second polysilicon layer 108, which can perform thefunctionality of a gate electrode. The hard mask 109 represents aprotective layer, and a sufficiently thick side wall oxide layer of thememory transistor is produced by means of the first side wall oxidelayer 112 and the second side wall oxide layer 117.

However, the above-described method for forming logic transistors andmemory transistors with different side wall oxide thicknesses has anumber of drawbacks. As described above, two critical lithography stepsare required during the method, and even slight deviations in thesesteps lead to wide-ranging negative consequences for the functionalityof the arrangement. The execution of these two critical lithographysteps makes fabrication of the layer structure 118 complex andexpensive.

A further drawback of the fabrication method described is based on thefact that the gate patterning of the logic transistors, on the one hand,and of the memory transistors, on the other hand, are carried out in twoseparate method steps. The patterning of the memory transistors takesplace in the method step in which the layer structure 110 shown in FIG.1D is formed from the layer structure 106 shown in FIG. 1C. By contrast,the patterning of the logic transistors takes place in the method stepin which the layer structure 115 shown in FIG. 1G is formed from thelayer structure 113 shown in FIG. 1F. In practice, it is not possible toset absolutely identical conditions for these two method steps. However,it is important to provide structures with a homogenous surface coveragedensity in the logic region, on the one hand, and in the memory region,on the other hand. The surface coverage density is defined as the ratioof the sum of the areas which are covered in the logic or memory regiondivided by the total surface area of the logic region or of the memoryregion. The surface coverage density should ideally be as homogenous aspossible over the entire chip, in order to be able to ensure minimaltolerances during fabrication of the gate electrodes.

If the surface coverage densities achieved by the two above-describedmethod steps for patterning of the logic transistors, on the one hand,and the memory transistors, on the other hand, deviate from one another,the result will be a variation in the geometry of the gate electrode.Adverse effects which result from an uneven surface coverage density arereferred to as etch loading effects. These have an adverse effect on thefunctionality of the integrated circuit formed. Therefore, the qualityof the transistors which are fabricated using the method described isoften poor.

U.S. Pat. No. 5,291,052 discloses a CMOS semiconductor device with ap-MOS transistor and with an n-MOS transistor on a wafer.

U.S. Pat. No. 6,160,317 discloses a method for fabricating asemiconductor device which allows etching of a field oxide whileminimizing damage to the silicon.

German Patent No. DE 196 54 738 A1 discloses a method for fabricating asemiconductor memory device with n-MOS and p-MOS transistors withdifferent properties.

Great Britain Patent No. GB 2,359,662 discloses a semiconductor devicewith a DRAM cell.

Accordingly, there is an need to overcome the problem of providinglaterally delimited layer sequences with different side wall thicknesseson a common substrate with a reduced level of outlay and in an improvedquality.

SUMMARY

The present invention is defined by the following claims, and nothing inthis section should be taken as a limitation on those claims. By way ofintroduction, the preferred embodiments described below relate to amethod for fabricating a layer arrangement, by a layer arrangement andby a memory arrangement.

A method is provided for fabricating a layer arrangement in which atleast one first layer sequence, which is in each case laterallydelimited, is formed on a first surface region of a substrate, and atleast one second layer sequence, which is in each case laterallydelimited, is formed on a second surface region of the substrate.Furthermore, in each case one first side wall layer having a firstthickness and comprising a first electrically insulating material isformed on at least one sub-region of the side walls of the first andsecond layer sequences. Furthermore, in each case one second side walllayer having a second thickness and comprising a second electricallyinsulating material is formed on at least one sub-region of the firstside wall layers of the first and second layer sequences. Then, thesecond side wall layers are removed from the first layer sequences.

This clearly allows the procedure to be simplified in particular whengate electrodes with different side wall oxide thicknesses are beingfabricated.

The first layer sequence on the first surface region of the substratemay be a logic transistor of a logic circuit, and the second layersequence may be a memory transistor in a memory region of an integratedcircuit. In the layer arrangement which has been fabricated inaccordance with the disclosed embodiments, the thickness of the sidewall oxide of the first laterally delimited layer sequence (layer havingthe first thickness) is less than the thickness of the side wall layeron the second laterally delimited layer sequence (layer having the firstthickness plus layer having the second thickness). On account of the lowthickness of the side wall oxide, the first layer sequence, whichpreferably forms a logic transistor in the logic region of an integratedcircuit, has a sufficiently low connection resistance and ensures asufficiently fast logic. By contrast, the second layer sequence has athicker side wall layer, resulting in a number of advantageous effects:a memory transistor with a high side wall oxide thickness has asufficiently long hold time for the stored information, and furthermorea sufficiently thick side wall oxide layer provides good protection fora memory transistor against any disruptive influence from itssurroundings.

According to an advantageous configuration of the method, the formationof at least one first layer sequence, which is in each case laterallydelimited, on the first surface region of the substrate and theformation of the at least one second layer sequence, which is in eachcase laterally delimited, on the second surface region of the substrateincludes the following sub-steps:

In a first sub-step, a first, electrically insulating auxiliary layer isformed on the first and second surface regions of the substrate, asecond, electrically conductive auxiliary layer is formed on the first,electrically insulating auxiliary layer, and a third, electricallyinsulating auxiliary layer is formed on the second, electricallyconductive auxiliary layer. In a second sub-step, the first, second andthird auxiliary layers are removed from the first surface region of thesubstrate. In a third sub-step, a fourth, electrically insulatingauxiliary layer is formed on the first and second surface regions of thesubstrate (or more specifically on the surface of the layer structure asobtained after the second sub-step), a fifth, electrically conductiveauxiliary layer is formed on the fourth, electrically insulatingauxiliary layer, and a sixth, electrically insulating auxiliary layer isformed on the fifth, electrically conductive auxiliary layer. In afourth sub-step, the fifth and sixth auxiliary layers on the first andsecond surface regions are jointly patterned in such a manner that theat least one laterally delimited first layer sequence is formed on thefirst surface region. In a fifth sub-step, the second, third and fourthauxiliary layers on the second surface region are patterned in such amanner that as a result the at least one second layer sequence, which isin each case laterally delimited, is formed on the second surfaceregion.

It should be emphasized that in the fourth sub-step the fifth and sixthauxiliary layers on the first and second surface regions are patternedtogether. In other words, in this sub-step, the layer sequences whichhave been deposited on the surface region are patterned in such a mannerthat as a result the lateral delimitation of the first and second layersequences is defined in a common method step. In other words, referringto a preferred exemplary embodiment in which the first layer sequencesare logic transistors and the second layer sequences are memorytransistors of an integrated circuit, both the logic transistors and thememory transistors are structurally defined in a single, common criticallithography step. This eliminates the need for one critical lithographystep compared to the method described above with reference to FIGS.1A-1I for the formation of logic transistors and memory transistors withdifferent side wall thicknesses, and consequently the method forfabricating logic transistors and memory transistors with different sidewall thicknesses is significantly simplified. As a result, thefabrication costs are reduced and the work involved is also reduced.

Furthermore, the fact that the logic transistors and the memorytransistors are patterned together means that etch loading effectsresulting from inhomogeneous surface coverage densities on differentsurface regions of the substrate (cf. description above) are reduced.Obviously, the uniformity of the surface coverage density of the firstand second layer sequences is improved, since the method parameters usedto form the first and second layer sequences are identical on account ofa common lithography step being used. Significant parameters of thelayer sequences, for example the length of the gate oxide region of theMOS transistors, are therefore identical for the logic transistors andmemory transistors, with the result that an integrated circuit withlogic region and memory region which has been fabricated using thedisclosed method is of improved quality compared to the prior art.

According to an advantageous configuration of the fabrication disclosedmethod, doping atoms are introduced into surface regions which adjointhe lateral end sections of the second layer sequences between the stepof forming the second side wall layer having the second thickness andcomprising the second electrically insulating material on at least onesub-region of the first side wall layers of the first and second layersequences, on the one hand, and the step of removing the second sidewall layers from the first layer sequences, on the other hand.

In other words, in this method step LDD regions are formed in thosesurface regions of the substrate which adjoin the lateral edge regionsof the second layer sequences. The objective of this method step is toform the first or second source/drain region of the second layersequences in a situation in which the second layer sequences are memorytransistors.

According to a refinement of the disclosed method, after the removal ofthe second side wall layers from the first layer sequences, doping atomsare introduced into surface regions of the substrate which are spatiallydecoupled from the lateral edge sections of the second layer sequencesand which partially overlap one of the surface regions of the substrateinto which doping atoms have been introduced.

This method step represents the step of forming HDD (highly doped drain)regions which are formed to overlap the LDD (lightly doped drain)regions described above. The concentration of the doping atoms is lowerin the LDD regions than in the HDD regions. The doping atoms may ben-type doping atoms or p-type doping atoms.

According to a further configuration, doping atoms are introduced intosurface regions of the substrate which adjoin lateral edge sections ofthe first layer sequences after the second side wall layers have beenremoved from the first layer sequences.

As described above, the first layer sequences are used in particular aslogic transistors in a logic region of an integrated circuit. In themethod step described, the first source/drain region and the secondsource/drain region of the logic transistors are formed. The dopingatoms which are introduced into surface regions of the substrates whichadjoin the lateral edge regions of the first layer sequence in this stepmay be n-doping atoms or p-doping atoms.

The method steps described can all be implemented using standardizedsemiconductor technology processes, such as the ion implantationprocess, known lithography processes and known etching processes, andknown deposition processes, such as for example the CVD (chemical vapordeposition) process. Therefore, the disclosed fabrication method isinexpensive and technologically simple.

According to another method for fabricating a layer arrangement, atleast one first layer sequence, which is in each case laterallydelimited, is formed on a first surface region of a substrate, and atleast one second layer sequence, which is in each case laterallydelimited, is formed on a second surface region of the substrate.Furthermore, in each case a first side wall layer having a firstthickness and comprising a first electrically insulating material isformed on at least one sub-region of the side walls of the first andsecond layer sequences. Furthermore, an auxiliary side wall layer isformed on at least one sub-region of the first side wall layers of thefirst layer sequence, and a second side wall layer having a secondthickness and comprising a second electrically insulating material isformed on at least one sub-region of the first side wall layer of thesecond layer sequence. The material used for the auxiliary side walllayer is selected in such a manner that while the second side wall layeris being formed on at least one sub-region of the first side wall layerof the second layer sequence, the auxiliary side wall layer remainsuncovered by the second electrically insulating material.

Evidently, the first layer sequence is protected from being covered bythe second side wall layer by the application of the auxiliary side walllayer. After the second side wall layer has been applied to the secondlayer sequence, the auxiliary side wall layer can be removed, with theresult that only the first side wall layer remains on the side wall ofthe first layer sequence, while the first and second side wall layersremain on the side wall of the second layer stack.

After the second side wall layer has been formed, it is preferable forthe auxiliary side wall layer to be removed from the first layer stack.

According to a preferred configuration, the second side wall layer isformed by means of thermal oxidation of at least part of the material ofthe second laterally delimited layer sequence. As a result of a suitableselection of materials, this thermal oxidation clearly acts “through”the first side wall layer. During the thermal oxidation, the auxiliaryside wall layer evidently protects the first layer sequence from thermaloxidation.

It is preferable for the first and second electrically insulatingmaterials to be silicon dioxide and for the material of the auxiliaryside wall layer to be silicon nitride.

The disclosed layer arrangement is described in more detail below.Configurations of the layer arrangement also apply to the methods usedto fabricate a layer arrangement.

The disclosed layer arrangement has a substrate, at least one firstlayer sequence, which is in each case laterally delimited, on a firstsurface region of the substrate, at least one second layer sequence,which is in each case laterally delimited, on a second surface region ofthe substrate, in each case one first side wall layer having a firstthickness and comprising a first electrically insulating material on atleast one sub-region of each of the side walls of each of the first andsecond layer sequences, and in each case one second side wall layerhaving a second thickness and comprising a second electricallyinsulating material on at least one sub-region of each of the first sidewall layers of each of the second layer sequences.

In particular, the first thickness may be less than the secondthickness. The first thickness is preferably between 5 nm and 7 nm,whereas the second thickness is preferably approximately 10 nm or above.

The substrate is preferably a silicon substrate, such as for example asilicon wafer or a silicon chip.

An insulation layer comprising a third electrically insulating materialmay be arranged between the substrate and at least part of the firstand/or second layer sequence.

Referring now to the use of the disclosed layer arrangement as a logicregion (first layer sequences) and memory region (second layersequences), it is possible for the insulation layer arranged between thelayer sequences and the substrate to form the gate oxide layer of thetransistors formed by the layer sequences.

According to an advantageous configuration of the layer arrangementaccording to the disclosed embodiments, the first layer sequenceincludes a first part-layer comprising a first electrically conductivematerial and a second part-layer comprising a fourth electricallyinsulating material.

The second layer sequence preferably includes a charge-storagepart-layer, a second part-layer comprising a fifth, electricallyinsulating material, a third part-layer comprising a second,electrically conductive material and a fourth part-layer comprising asixth, electrically insulating material.

In particular, the charge-storage part-layer may be a layer comprisingpolycrystalline silicon with a silicon dioxide-silicon nitride-silicondioxide layer sequence (ONO layer) as covering layer. Alternatively, thecharge-storage part-layer may be a silicon dioxide-siliconnitride-silicon dioxide layer sequence (ONO layer).

The two alternatives described correspond to two different concepts ofmemory transistors, namely memory transistors based on the floating gateprinciple and memory transistors having an ONO layer as charge-storagelayer. Both floating gate memory transistors and ONO-layer memorytransistors can be used as second layer sequences of the layerarrangement.

In the case of an ONO memory transistor, the gate oxide layer isreplaced by an ONO layer (silicon dioxide-silicon nitride-silicondioxide), and charge carriers can be injected into the ONO layer (ormore specifically into the silicon nitride layer of the ONO layer),where they remain permanently, by means of channel hot electron (CHE)injection. The gate region of an ONO transistor has a differentelectrical conductivity depending on the number of electrons introducedinto the ONO layer. In this way, the memory information is coded in theONO layer.

By contrast, in the case of a floating gate memory transistor, a layercomprising an electrically conductive material, e.g. polycrystallinesilicon, and a sufficiently thick layer comprising an electricallyinsulating material are introduced between the gate electrode and thegate oxide layer. Charge carriers, whose presence changes the electricalconductivity of the channel region below the gate oxide between thesource region and the drain region of a transistor of this type, areinjected into the electrically conductive layer above the gate oxidelayer by means of Fowler-Nordheim tunneling or by means of hot chargecarriers as a result of a sufficiently high electric voltage beingapplied between the gate electrode and the source/drain regions. Thevalue of this conductivity codes the information stored in the floatinggate memory transistor.

The layer arrangement which is provided in accordance with the disclosedembodiments has the advantage that the second layer sequences which itincludes can optionally be configured as floating gate transistors, asONO transistors or as a different type of memory transistor. Therefore,the disclosed layer arrangement can easily and flexibly be matched tothe requirements of the specific application.

The first and/or second electrically conductive material is preferablypolycrystalline silicon.

The first, second, third, fourth, fifth and sixth electricallyinsulating materials may be silicon dioxide or silicon nitride or asilicon dioxide-silicon nitride-silicon dioxide layer sequence (ONOlayer).

In other words, an ONO layer can be used not only, as described above,as a layer for storing charge carriers, the number of which codes thelogic information stored in a memory transistor, but also as a layerwith electrically insulating properties, for example for decoupling twoelectrically conductive regions.

Finally, a memory arrangement is provided having a layer arrangementwith the features given in the above description. In the memoryarrangement, the at least one first layer sequence on the first surfaceregion of the substrate forms at least part a of the logic region of thememory arrangement, whereas the at least one second layer sequence onthe second surface region of the substrate forms at least a part of thememory cell region of the memory arrangement.

To summarize, the demand is satisfied for side wall oxide layers ofdifferent thicknesses in logic transistors and in memory transistors ina common integrated circuit which can be fabricated using only onecritical gate patterning step. Therefore, the method for fabricating alayer arrangement of this type is significantly simpler and lessexpensive than the method which is known from the prior art.Furthermore, the method achieves a homogenous surface coverage, whichhas advantageous effects on the reproducibility and quality of the gatepatterning. Moreover, etch loading effects are avoided as a result.

Clearly, one aspect can also be considered to lie in the fact that boththe first layer sequences and the second layer sequences are coveredwith a thin side wall oxide layer, and then the first and second layersequences are covered with a second, preferably thicker side wall oxidelayer, which second side wall oxide layer is then removed from the logicregion

Further aspects and advantages of the invention are discussed below inconjunction with the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1I show cross-sectional views through layer structures atdifferent times during a fabrication method according to the prior art,

FIGS. 2A-2J show cross-sectional views through layer structures atdifferent times during a fabrication method in accordance with apreferred exemplary embodiment of the method according to the inventionfor fabricating a layer arrangement,

FIGS. 3A-3E show cross-sectional views through layer structures atdifferent times during a fabrication method according to anotherpreferred exemplary embodiment of the method according to the inventionfor fabricating a layer arrangement.

DETAILED DESCRIPTION OF THE DRAWINGS AND PRESENTLY PREFERRED EMBODIMENTS

The text which follows, referring to FIG. 2A to FIG. 2J, describes apreferred exemplary embodiment of the method for fabricating a layerarrangement.

FIG. 2A to FIG. 2J each include a dashed vertical separation line. Thisseparates a first surface region 201 a of a substrate 201, which is ineach case shown to the left-hand side of the dividing line and on whichfirst layer sequences are produced to form logic transistors, from asecond surface region 201 b of the substrate 201, which is in each caseshown to the right of the dividing line and on which second layersequences are formed to produce memory transistors. To simplifyexplanation, only one first layer sequence on the first surface region201 a and only one second layer sequence on the second surface region201 b are shown in the figures. In practice, there will often in eachcase be a large number of layer sequences on the corresponding surfaceregions 201 a, 201 b.

The layer structure 200 shown in FIG. 2A is obtained by a first silicondioxide layer 202 being formed on a first surface region 201 a and on asecond surface region 201 b of a silicon wafer 201, a first polysiliconlayer 203 being formed on the first silicon dioxide layer 202 and an ONOlayer 204 being formed on the first polysilicon layer 203. The ONO layer204 includes a silicon dioxide part-layer 204 a, a silicon nitridepart-layer 204 b and a further silicon dioxide pail-layer 204 c. Thesilicon dioxide part-layer 204 a of the ONO layer 204 is formed on thefirst polysilicon layer 203, the silicon nitride part-layer 204 b isformed on the silicon dioxide part-layer 204 a and the further silicondioxide part-layer 204 c is formed on the silicon nitride part-layer 204b.

In accordance with the exemplary embodiment described, the first silicondioxide layer 202, the first polysilicon layer 203 and the ONO layer 204are formed using thermal oxidation or CVD (chemical vapor deposition)processes.

To produce the layer structure 205 shown in FIG. 2B, the first silicondioxide layer 202, the first polysilicon layer 203 and the ONO layer 204are removed from the first surface region 201 a of the silicon wafer201.

In accordance with the exemplary embodiment described, this method stepis carried out by using a suitable mask to cover the second surfaceregion of the layer structure 200 and then using a lithography processand an etching process to remove the first silicon dioxide layer 202,the first polysilicon layer 203 and the ONO layer 204 from the firstsurface region 201 a of the layer structure 200. The first surfaceregion 201 a represents what will subsequently be the logic region,whereas the second surface region 201 b forms what will subsequently bethe memory region of an integrated circuit. It should be emphasized thatthe lithography process step which is required to convert the layerstructure 200 into the layer structure 205 is not critical, i.e. slightstructural inaccuracies when the lithography process is carried out donot have any serious consequences for the functionality of theintegrated circuit obtained. Therefore, this method step is relativelysimple.

To produce the layer structure 206 shown in FIG. 2C, a second silicondioxide layer 207 is deposited on the first and second surface regions201 a, 201 b of the silicon wafer 201 (more specifically, this layer isnot deposited on the second surface region 201 b itself, but rather onthe surface of the topmost of the layers arranged on the second surfaceregion 201 b), a second polysilicon layer 208 is deposited on the secondsilicon dioxide layer 207, and a silicon nitride hard mask 209 isdeposited on the second polysilicon layer 208.

These method steps are likewise carried out using the CVD process, i.e.the layers 207, 208, 209 are deposited from the vapor phase.

The layer structure 210 shown in FIG. 2D is obtained by the secondpolysilicon layer 208 and the silicon nitride hard mask 209 on the firstand second surface regions 201 a, 201 b being patterned jointly in sucha manner that a laterally delimited, first layer sequence 212 is formedon the first surface region. As a result, a laterally delimitedauxiliary layer sequence 213 a is formed on the second surface region201 b.

To implement this method step, a lithography process and an etchingprocess are applied to the entire surface of the layer structure 206.Since these lithography processes and this etching process formlaterally delimited structures, the size of which is extremely small (ofthe order of magnitude of 100 nm and below), this lithography step iscritical. This means that even slight errors in this method step willhave a significant effect on the functionality of the integrated circuitwhich is fabricated. Therefore, particular attention is required in thismethod step. It should be emphasized that this method step representsthe only critical lithography step in the disclosed fabrication method.The fact that the same process conditions are present when the laterallydelimited regions 212, 213 a in the first and second surface regions arebeing formed means that fluctuations in the physical parameters of thestructures formed are avoided. In particular, the surface coveragedensity is homogenous.

To convert the layer structure 210 shown in FIG. 2D into the layerstructure 211 shown in FIG. 2E, the first polysilicon layer 203, the ONOlayer 204 and the second silicon dioxide layer 207 on the second surfaceregion 201 b of the silicon wafer 201 a re patterned in such a mannerthat as a result a second layer sequence 213, which is in each caselaterally delimited, is formed on the second surface region 201 b.

In this lithography method step, which is not critical, the firstsurface region 201 a, which will subsequently form the logic region, hasbeen covered with a mask. This means that the method step is appliedonly to the second surface region 201 b of the layer structure 210. Thepatterning of the layers 203, 204, 207 on the second surface region 201b is carried out using a suitable etching process, which is selected insuch a manner that the lateral delimitation of the auxiliary layersequence 213 a also defines the lateral delimitation during theetching-back of the layers 203, 204, 207 on the second surface region201 b. In other words, an anisotropic etch takes place in a verticaldirection in accordance with FIG. 2E, with the result that the lateraldelimitation defined by the auxiliary layer sequence 213 a obviouslycontinues downwards. Therefore, the lateral delimitation of the secondlaterally delimited layer sequence 213 is determined by the criticallithography step described above.

The method steps which have been described with reference to FIG. 2A toFIG. 2E can be combined to an extent which is such that a laterallydelimited first layer sequence 212 on the first surface region 201 a ofthe silicon water 201 and a laterally delimited second layer sequence213 on the second surface region 201 b of the silicon wafer 201 a reformed.

To convert the layer structure 211 shown in FIG. 2E into the layerstructure 214 shown in FIG. 2F, in each case a first silicon dioxideside wall layer 215 having a first thickness d1 is formed on the sidewalls of the first layer sequence 212 and of the second layer sequence213.

According to the exemplary embodiment described, this method step iscarried out by thermal oxidation of the side walls of the firstlaterally delimited layer sequence 212 and of the second laterallydelimited layer sequence 213. Thermal oxidation means that an oxygenatmosphere is generated in the process chamber and the reactivity of theoxygen is increased by raising the temperature. As a result, the sidewalls of the laterally delimited layer sequences 212, 213 which includesilicon are oxidized to form silicon dioxide. The result is a firstsilicon dioxide side wall layer 215, the first thickness d1 of which isapproximately 5 nm.

The layer structure 216 shown in FIG. 2G is obtained by in each caseforming a second silicon dioxide side wall layer 217 having a secondthickness d2 on the first silicon dioxide side wall layers 215 of thefirst layer sequence 212 and of the second layer sequence 213.

In accordance with the described preferred exemplary embodiment of themethod for fabricating a layer arrangement, the second silicon dioxideside wall layer 217 is made from silicon dioxide. The second silicondioxide side wall layer 217 is applied to the first silicon dioxide sidewall layers 215 using the CVD process.

According to the exemplary embodiment described, the second thickness d2is greater than the first thickness d1, i.e. d2>d1.

It should be emphasized that as an alternative to the exemplaryembodiment described, the second side wall layers may also be made fromsilicon nitride material, which can likewise be applied to the firstsilicon dioxide side wall layers 215 by means of a CVD process.

According to the exemplary embodiment described, the second silicondioxide side wall layers 217 are formed on the first silicon dioxideside wall layers 215 using a special CVD process, known as the TEOS(tetraethyl orthosilicate) process. To achieve a high wet-etching rateof the second silicon dioxide side wall layers 217, it is preferable touse a LPCVD (low pressure chemical vapor deposition) process. It shouldbe emphasized that a thermally grown silicon dioxide layer, such as thefirst silicon dioxide side wall layer 215, on the one hand, and asilicon dioxide layer which is applied using the TEOS CVD process, inparticular using the TEOS LPCVD process, (such as the second silicondioxide side wall layer 217), on the other hand, have different physicalproperties, in particular in terms of their interaction with etchingchemicals.

To achieve the layer structure 218 shown in FIG. 2H, doping atoms areintroduced into those surface regions of the silicon substrate 201 whichadjoin the lateral end sections of the second layer sequence 213, withthe result that the LDD regions 219 are formed.

According to the described exemplary embodiment of the method forfabricating a layer arrangement, this method step is carried out usingan ion implantation process. This is understood as meaning theintroduction of foreign atoms into the surface of a solid body bybombarding the solid body with accelerated ions. By means of ionimplantation, it is possible to influence the electrical properties ofthe semiconductor material, in particular to increase the electricalconductivity. The ions are fired onto the second surface region 201 b ofthe layer structure 216 with a predetermined energy and penetrate intothe substrate in its boundary regions with respect to the secondlaterally delimited layer sequence 213. As shown in FIG. 2H, thisresults in LDD regions 219, which according to the exemplary embodimentdescribed are n-doped. These regions are provided for the purpose offorming part of the source/drain regions of what will subsequently bethe memory transistor. The concentration of the doping atoms in the LDD(lightly doped drain) regions 219 is referred to below as the firstcharge carrier density.

To convert the layer structure 218 shown in FIG. 2H into the layerstructure 220 shown in FIG. 2I, the second silicon dioxide side walllayer 217 is removed from the first laterally delimited layer sequence212.

For this purpose, the sub-region of the layer structure 218 to the rightof the dashed line, i.e. the region of the memory transistors, iscovered with a mask, whereas the region to the left of the dashed line,i.e. the logic region, is treated using a wet-chemical etching process.This patterning step is once again not critical. The second silicondioxide side wall layer 217 is removed from the first laterallydelimited layer sequences 212 using a suitable wet-chemical etchingprocess, with the result that only the first silicon dioxide side walllayer 215 remains in place on the side wall of the first laterallydelimited layer sequences 212. The selectivity of the etching process isexploited in the wet-etching process. With regard to the materialconstellation of the layer structure 218, use is made of the fact thatwet-chemical etching, using hydrofluoric acid (HF), of the secondsilicon dioxide side wall layer 217 formed using a CVD process has asignificantly higher etching rate than the wet-chemical etching of thefirst silicon dioxide side wall layer 215 formed by means of thermaloxidation. The ratio of the etching rates of CVD silicon dioxide tothermally grown silicon dioxide in the case of wet-chemical etchingusing hydrofluoric acid is approximately ten to one. This ensures thatthe etching process is ended sufficiently reliably after the secondsilicon dioxide side wall layer 217 has been etched away, whereasundesirable further etching of the first silicon dioxide side wall layer215 in the first laterally delimited layer sequence 212 is substantiallyavoided.

An alternative way of carrying out the disclosed method a forfabricating a layer arrangement should also be pointed out. In themethod step described above with reference to FIG. 2G, in which thesecond silicon dioxide side wall layers 217 are formed on the firstsilicon dioxide side wall layers 215 of the first and second layersequences 212, 214, as an alternative to silicon dioxide (SiO2), it isalso possible to use silicon nitride (Si3N4) as material for the secondsilicon dioxide side wall layers 217. In such a scenario, the firstsilicon dioxide side wall layer 215 is produced from thermally grownsilicon dioxide, whereas the second side wall layer 217 is produced fromsilicon nitride which is applied to the first silicon dioxide side walllayer 215 using a suitable CVD process. In such a case, phosphoric acid(H3PO4) instead of hydrofluoric acid is a suitable chemical for thewet-chemical etching process by means of which the layer structure 220shown in FIG. 2I is produced from the layer structure 218 shown in FIG.2H. In this case, use is made of the fact that silicon nitride is etchedat a significantly higher etching rate than silicon dioxide whenphosphoric acid is used. The ratio of the wet-etching rates of siliconnitride which has been grown using a CVD process and silicon dioxideproduced by means of thermal oxidation is greater than two to one.Therefore, if silicon nitride is used as material for the second sidewall layer 217, the wet etch of the side wall of the first layersequence 212 is guaranteed to stop with sufficient reliability after thesecond side wall layer 217 made from silicon nitride has been completelyremoved.

To convert the layer structure 220 shown in FIG. 2I into the layerarrangement 221 shown in FIG. 2J, doping atoms having a second chargecarrier density are introduced into surface regions of the silicon wafer201 which are spatially decoupled from the lateral end sections of thesecond laterally delimited layer sequence 213 and which partiallyoverlap the LDD regions 219 of the silicon wafer 201. As a result, theHDD (highly doped drain) regions 222 are formed. Furthermore, dopingatoms having a third charge carrier density are introduced into surfaceregions of the silicon wafer 201 which adjoin the lateral end sectionsof the first laterally delimited layer sequence 212, with the resultthat the doped regions 223 are formed.

According to the described exemplary embodiment of the fabricationmethod, the described method steps by means of which the layerarrangement 221 is obtained from the layer structure 220 are carried outby using an ion implantation process. It should be noted that the secondcharge carrier density of doping atoms in the HDD regions 222 is higherthan the first charge carrier density of doping atoms in the first LDDregions 219. The HDD regions 222 or the doped regions 223 can be formedeither in a common method step or in two separate method steps.

The product obtained from the described method for fabricating a layerarrangement is a preferred exemplary embodiment of the layer arrangement221, having a silicon wafer 201, having a laterally delimited firstlayer sequence 212 on a first surface region 201 a of the silicon wafer201, having a laterally delimited second layer sequence 213 on a secondsurface region 201 b of the silicon wafer 201, having a first silicondioxide side wall layer 215 of thickness d1 on the side walls of thefirst and second layer sequences 212, 213 and having a second silicondioxide side wall layer 217 of the second thickness d2 on the firstsilicon dioxide side wall layers 215 of the second laterally delimitedlayer sequence 213.

Between the silicon wafer 201 and the first laterally delimited layersequence 212, the electrically insulating second silicon dioxide layer207 is arranged on the first surface region 201 a of the silicon wafer201, and between the silicon wafer 201 and the second laterallydelimited layer sequence 213 an electrically insulating first silicondioxide layer 202 is arranged on the second surface region 201 b of thesilicon wafer 201. The second laterally delimited layer sequence 213includes a charge-storage part-layer which is formed as a firstpolysilicon layer 203, the ONO layer 204, the second silicon dioxidelayer 207, the second polysilicon layer 208 and the silicon nitride hardmask 209. The first laterally delimited layer sequence 212 includes thesecond polysilicon layer 208 and the silicon nitride hard mask 209.

The left-hand region of FIG. 2J can be used as a logic transistor of alogic region of an integrated circuit, whereas the right-hand region ofthe layer arrangement 221 from FIG. 2J can be used as a memorytransistor of a memory region of an integrated circuit. The firstlaterally delimited layer sequence 212, together with the doped regions223, forms a logic transistor which includes a side wall layer which isformed as a first silicon dioxide side wall layer 215 and has asufficiently small thickness d1 for the logic transistor to besufficiently fast and to have a sufficiently low connection resistance.In this case, the doped regions 223 function as first and secondsource/drain regions, the second silicon dioxide layer 207 functions asa gate oxide layer and the second polysilicon layer 208 functions as agate electrode.

By contrast, the memory transistor in the right-hand region of the layerarrangement 221 shown in FIG. 2J, which is formed by the secondlaterally delimited layer sequence 213 and the LDD regions 219 and theHDD regions 222, includes a sufficiently thick side wall layer, whichhas been formed from the first silicon dioxide side wall layer 215 andthe second silicon dioxide side wall layer 217, of approximate thicknessd1+d2 and is therefore sufficiently reliably shielded from itssurroundings. In the right-hand region of the layer arrangement 221,which is formed as a memory transistor, the LDD regions 219 and the HDDregions 222 function as first and second source/drain regions, the firstsilicon dioxide layer 202 functions as a gate oxide layer, the firstpolysilicon layer 203 functions as a charge-storage layer, into whichelectrical charge carriers can be injected permanently, for example bymeans of Fowler-Nordheim tunneling or hot electrons, the ONO layer 204and the second silicon dioxide layer 207 function as an electricallyinsulating layer between the charge-storage layer 203 and the secondpolysilicon layer 208, the arrangement comprising the layers 204, 207being sufficiently thick to ensure a sufficiently long hold time for theinformation stored in the first polysilicon layer 203, the secondpolysilicon layer 208 functions as a gate electrode and the siliconnitride hard mask 209 functions as a protective layer.

The text which follows, referring to FIGS. 3A to 3E, describes anotherpreferred exemplary embodiment of the method for fabricating a layerarrangement.

According to the exemplary embodiment described below, the method stepswhich have been described with reference to FIG. 2A to FIG. 2F areidentical to those used in the method which has been described withreference to FIG. 2A to FIG. 2J.

The layer structure 300 shown in FIG. 3A is obtained by, starting fromthe layer structure 214 shown in FIG. 2F, depositing a first auxiliarylayer 301 comprising silicon nitride over the entire surface of thelaterally delimited layer sequences of the logic region (on theleft-hand side of the figure) and of the memory region (on theright-hand side of the figure). Then, by way of example, a second,silicon dioxide auxiliary layer 302 is deposited on the first, siliconnitride auxiliary layer 301.

To obtain the layer structure 303 shown in FIG. 3B, the left-handsurface region of the substrate 201, in accordance with FIG. 3B, islithographically covered using a suitable mask, and the second, silicondioxide auxiliary layer 302 and the first, silicon nitride auxiliarylayer 301 are removed from the laterally delimited layer sequence on theright-hand side of FIG. 3B. The second, silicon dioxide auxiliary layer302 is removed using a wet-chemical etching process. Then, thephotoresist is removed from the surface of the layer structure and thefirst, silicon nitride auxiliary layer 301 is removed using awet-chemical etching process employing hot phosphoric acid. Thesub-region of the layer structure which is on the left-hand side of FIG.3B, however, is protected against the first, silicon nitride auxiliarylayer 301 being removed. This is based on the high selectivity achievedwhen etching with hot phosphoric acid, i.e. this chemical is effectiveat etching silicon nitride, whereas silicon dioxide is protected againstbeing etched.

To obtain the layer structure 304 shown in FIG. 3C, the second silicondioxide auxiliary layer 302 is removed from the surface region of thesilicon substrate 201 which is on the left-hand side of FIG. 3C. This isachieved by using an etching process with dilute hydrofluoric acid, thehigh selectivity achieved when etching using hydrofluoric acid forsilicon dioxide produced by means of thermal oxidation, on the one hand,and silicon dioxide produced, for example, using an ozone-activateddeposition process, on the other hand, advantageously being employed. Inother words, by using dilute hydrofluoric acid, it is possible to removesilicon dioxide, which has been applied using, for example, anozone-activated deposition process and which has not yet been densifiedby means of a high-temperature process, with a high etching rate. Bycontrast, silicon dioxide produced by means of thermal oxidation isremoved at a much lower etching rate when dilute hydrofluoric acid isused.

To obtain the layer structure 305 shown in FIG. 3D, a second silicondioxide side wall layer 306 is formed on the laterally delimited layersequence on the right-hand side of FIG. 3D by means of thermaloxidation. It should be noted that the laterally delimited layersequence on the left-hand side of FIG. 3D is protected from thermaloxidation, since the first, silicon nitride auxiliary layer 301 acts asan oxidation barrier. Obviously, on account of the materialconfiguration selected (thermally oxidized silicon dioxide/siliconnitride), the first, silicon nitride auxiliary layer 301 acts as aprotective layer protecting against the formation of a thermallyoxidized silicon dioxide region.

To obtain the layer structure 307 shown in FIG. 3E, the first, siliconnitride auxiliary layer 301 is removed from the laterally delimitedlayer sequence on the left-hand side of FIG. 3E using a suitablewet-chemical etching process. By contrast, on account of the highetching selectivity (once again in hot phosphoric acid, for example),the second silicon dioxide side wall layer 306 and the first silicondioxide side wall layer 215 of the laterally delimited layer sequenceson the right-hand and left-hand sides of FIG. 3E are not attacked by theetchant.

The result is the layer structure 307 shown in FIG. 3E. The laterallydelimited layer sequence on the left-hand side of FIG. 3E has beenprovided with a thin side wall oxide layer (only the first silicondioxide side wall layer 215), whereas the laterally delimited layersequence on the right-hand side of FIG. 3E has been covered with a thickside wall oxide layer (formed by the first silicon dioxide side walllayer 215 and the second silicon dioxide side wall layer 306).

It should be noted that—in particular if the layer structure 307 is usedas an arrangement for field-effect transistors—doped surface regions ofthe substrate 201 which adjoin the laterally delimited layer sequencesmay be required. Doped regions of this type may be formed at a suitablepoint during the fabrication method, for example using an ionimplantation process.

It is therefore intended that the foregoing detailed description beregarded as illustrative rather than limiting, and that it be understoodthat it is the following claims, including all equivalents, that areintended to define the spirit and scope of this invention.

1. A method for fabricating a layer arrangement, comprising: (a) formingat least one first layer sequence, each of which is laterally delimitedby a first side wall, at least as part of a logic region of a memoryarrangement, on a first surface region of a substrate, and forming atleast one second layer sequence, each of which is laterally delimited bya second side wall, at least as part of a memory cell region of thememory arrangement, on a second surface region of the substrate; (b)forming a first side wall layer having a first thickness and comprisinga first electrically insulating material in at least one sub-region ofthe first and second side walls of the first and second layer sequencesby means of thermal oxidation of the at least one sub-region of thefirst and second side walls of the first and second layer sequences,wherein the first side wall layer is formed by thermal oxidation suchthat a second side wall layer formed thereon has different physicalproperties than the first side wall layer; (c) forming the second sidewall layer having a second thickness and comprising a secondelectrically insulating material on at least one sub-region of the firstside wall layers of the first and second layer sequences; and (d)removing the second side wall layer completely from the at least onefirst layer sequence; and (e) forming doped regions of the substrateproximate to one of the first surface region or the second surfaceregion.
 2. The method according to claim 1, wherein (a) furthercomprises: (a1) forming a first, electrically insulating auxiliary layeron the first and second surface regions of the substrate, forming asecond, electrically conductive auxiliary layer on the first,electrically insulating auxiliary layer, and forming a third,electrically insulating auxiliary layer on the second, electricallyconductive auxiliary layer; (a2) removing the first, second and thirdauxiliary layers from the first surface region of the substrate; (a3)forming a fourth, electrically insulating auxiliary layer on the firstand second surface regions of the substrate, forming a fifth,electrically conductive auxiliary layer on the fourth, electricallyinsulating auxiliary layer, and forming a sixth, electrically insulatingauxiliary layer on the fifth, electrically conductive auxiliary layer;(a4) patterning, jointly, the fifth and sixth auxiliary layers on thefirst and second surface regions in such a manner that the at least onelaterally delimited first layer sequence is formed on the first surfaceregion; (a5) Patterning, on the second surface region, the second, thirdand fourth auxiliary layers such that the at least one second layersequence, being laterally delimited, is formed on the second surfaceregion.
 3. The method according to claim 1 wherein (e) furthercomprises: (e1) introducing doping atoms into surface regions of thesubstrate which adjoin the lateral end sections of the second layersequence, after (c) and before (d) and introducing doping atoms intosurface regions of the substrate which adjoin the lateral end sectionsof the first layer sequence after (d).
 4. The method according to one ofclaim 1, wherein (e) further comprises: (e1) introducing doping atomsinto surface regions of the substrate which adjoin the lateral endsections of the first layer sequence.
 5. A layer arrangement comprising:a substrate; at least one first layer sequence, each of which islaterally delimited by a first side wall, at least as part of a logicregion of a memory arrangement, on a first surface region of thesubstrate; at least one second layer sequence, each of which islaterally delimited by a second side wall, at least as part of a memorycell region of the memory arrangement, on a second surface region of thesubstrate; a first side wall layer having a first thickness andcomprising a first electrically insulating material in at least onesub-region of each of the first and second side walls of each of thefirst and second layer sequences, the first side wall layer being formedby means of thermal oxidation of the at least one sub-region of each ofthe first and second side walls of each of the first and second layersequences; a second side wall layer having a second thickness andcomprising a second electrically insulating material on at least onesub-region of each of the first side wall layers of each of the secondlayer sequences, the second side wall layers being absent from the firstside wall layers of each of the first layer sequences, wherein the firstside wall layer has different physical properties than the second sidewall layer formed thereon; and doped regions formed in the substrateproximate to at least the first surface region, the doped regionproximate to the first surface region having been formed after removalof the second sidewall layers from the first side wall layers of each ofthe at least one first layer sequences.
 6. The method for fabricating alayer arrangement according to claim 1, wherein the second side wall isformed by means of a CVD process and the second side wall layer isremoved from the at least one first layer sequence by means of selectiveetching due to different physical properties of the first and secondside wall layers in terms of their interaction with etching chemicals.7. The method according to claim 2, wherein (e) further comprisesfurther: (e1) introducing doping atoms into surface regions of thesubstrate which adjoin the lateral end sections of the second layersequences, after (c) and before (d) and introducing doping atoms intosurface regions of the substrate which adjoin the lateral end sectionsof the first layer sequence after (d).
 8. The method according to one ofclaim 2, wherein (e) further comprises: (e1) introducing doping atomsinto surface regions of the substrate which adjoin the lateral endsections of the first layer sequence.
 9. The method according to claim3, further comprising subsequent to (d): (f) introducing doping atomsinto surface regions of the substrate which are spatially decoupled fromthe lateral end sections of the second layer sequences and whichpartially overlap those surface regions of the substrate into whichdoping atoms have been introduced.
 10. A method for fabricating a layerarrangement, comprising: (a) forming at least one first layer sequence,each of which is laterally delimited by a first side wall, on a firstsurface region of a substrate, and forming at least one second layersequence, each of which is laterally delimited by a second side wall, ona second surface region of the substrate; (b) forming a first side walllayer having a first thickness and comprising a first electricallyinsulating material on at least one sub-region of the first and secondside walls of the first and second layer sequences; (c) forming anauxiliary side wall layer on at least one sub-region of the first sidewall layers of the first layer sequence; (d) forming a second side walllayer having a second thickness and comprising a second electricallyinsulating material on at least one sub-region of the first side walllayer of the second layer sequence, the material used for the auxiliaryside wall layer being selected such that, while the second side walllayer is being formed on at least one sub-region of the first side walllayer of the second layer sequence, the auxiliary side wall layerremains uncovered by the second electrically insulating material. 11.The method according to claim 10, further comprising: (e) removing theauxiliary side wall layer from the first layer stack.
 12. The methodaccording to claim 10, in which the second side wall layer is formed bymeans of thermal oxidation of at least part of the material of thesecond laterally delimited layer sequence.
 13. The method according toone of claim 10, in which the first and second electrically insulatingmaterials are silicon dioxide, and in which the material used for theauxiliary side wall layer is silicon nitride.
 14. A memory arrangementhaving the layer arrangement according to one of claim 10, wherein: theat least one first layer sequence on the first surface region of thesubstrate forms at least part of the logic region of the memoryarrangement; and the at least one second layer sequence on the secondsurface region of the substrate forms at least part of the memory cellregion of the memory arrangement.
 15. The method according to claim 11,in which the second side wall layer is formed by means of thermaloxidation of at least part of the material of the second laterallydelimited layer sequence.
 16. The method according to one of claim 11,in which the first and second electrically insulating materials aresilicon dioxide, and in which the material used for the auxiliary sidewall layer is silicon nitride.
 17. A memory arrangement having the layerarrangement according to one of claim 11, wherein: the at least onefirst layer sequence on the first surface region of the substrate formsat least part of the logic region of the memory arrangement; and the atleast one second layer sequence on the second surface region of thesubstrate forms at least part of the memory cell region of the memoryarrangement.
 18. The method according to one of claim 12, in which thefirst and second electrically insulating materials are silicon dioxide,and in which the material used for the auxiliary side wall layer issilicon nitride.
 19. A memory arrangement having the layer arrangementaccording to one of claim 12, wherein: the at least one first layersequence on the first surface region of the substrate forms at leastpart of the logic region of the memory arrangement; and the at least onesecond layer sequence on the second surface region of the substrateforms at least part of the memory cell region of the memory arrangement.20. A memory arrangement having the layer arrangement according to oneof claim 13, wherein: the at least one first layer sequence on the firstsurface region of the substrate forms at least part of the logic regionof the memory arrangement; and the at least one second layer sequence onthe second surface region of the substrate forms at least part of thememory cell region of the memory arrangement.
 21. A memory arrangementhaving the layer arrangement according to one of claim 5, wherein: theat least one first layer sequence on the first surface region of thesubstrate forms at least part of the logic region of the memoryarrangement; and the at least one second layer sequence on the secondsurface region of the substrate forms at least part of the memory cellregion of the memory arrangement.
 22. The layer arrangement according toclaim 5, wherein the first thickness is less than the second thickness.23. The layer arrangement according to claim 5, wherein the firstthickness is between approximately 5 nm and 7 nm.
 24. The layerarrangement according to one of claim 5, wherein the second thickness isapproximately 10 nm or above.
 25. The layer arrangement according to oneof claim 5, wherein the substrate is one of a silicon wafer or a siliconchip.
 26. The layer arrangement according to one of claim 5, furthercomprising an insulation layer comprising a third electricallyinsulating material is arranged on at least part of the surface of thesubstrate located between the substrate and at least part of the firstand/or second layer sequences.
 27. The layer arrangement according toone of claim 5, wherein the first layer sequence further comprises afirst part-layer comprising a first electrically insulating material anda second part-layer comprising a fourth electrically insulatingmaterial.
 28. The layer arrangement according to one of claim 5, whereinthe second layer sequence further comprises a charge-storage part-layer,a second part-layer comprising a fifth, electrically insulatingmaterial, a third part-layer comprising a second, electricallyconductive material and a fourth part-layer comprising a sixth,electrically insulating material.
 29. A layer arrangement according toclaim 5, wherein the first and second side wall layers have differentphysical properties in terms of their interaction with etchingchemicals.
 30. The layer arrangement according to claim 22, wherein thefirst thickness is between approximately 5 nm and 7 nm.
 31. The layerarrangement according to one of claim 22, wherein the second thicknessis approximately 10 nm or above.
 32. The layer arrangement according toone of claim 22, wherein the substrate is one of a silicon wafer or asilicon chip.
 33. The layer arrangement according to one of claim 22,further comprising an insulation layer comprising a third electricallyinsulating material is arranged on at least part of the surface of thesubstrate located between the substrate and at least part of the firstand/or second layer sequences.
 34. The layer arrangement according toone of claim 22, wherein the first layer sequence further comprises afirst part-layer comprising a first electrically insulating material anda second part-layer comprising a fourth electrically insulatingmaterial.
 35. The layer arrangement according to one of claim 22,wherein the second layer sequence further comprises a charge-storagepart-layer, a second part-layer comprising a fifth, electricallyinsulating material, a third part-layer comprising a second,electrically conductive material and a fourth part-layer comprising asixth, electrically insulating material.
 36. A memory arrangement havingthe layer arrangement according to one of claim 22, wherein: the atleast one first layer sequence on the first surface region of thesubstrate forms at least part of the logic region of the memoryarrangement; and the at least one second layer sequence on the secondsurface region of the substrate forms at least part of the memory cellregion of the memory arrangement.
 37. The layer arrangement according toone of claim 23, wherein the second thickness is approximately 10 nm orabove.
 38. The layer arrangement according to one of claim 23, whereinthe substrate is one of a silicon wafer or a silicon chip.
 39. The layerarrangement according to one of claim 23, further comprising aninsulation layer comprising a third electrically insulating material isarranged on at least part of the surface of the substrate locatedbetween the substrate and at least part of the first and/or second layersequences.
 40. The layer arrangement according to one of claim 23,wherein the first layer sequence further comprises a first part-layercomprising a first electrically insulating material and a secondpart-layer comprising a fourth electrically insulating material.
 41. Thelayer arrangement according to one of claim 23, wherein the second layersequence further comprises a charge-storage part-layer, a secondpart-layer comprising a fifth, electrically insulating material, a thirdpart-layer comprising a second, electrically conductive material and afourth part-layer comprising a sixth, electrically insulating material.42. A memory arrangement having the layer arrangement according to oneof claim 23, wherein: the at least one first layer sequence on the firstsurface region of the substrate forms at least part of the logic regionof the memory arrangement; and the at least one second layer sequence onthe second surface region of the substrate forms at least part of thememory cell region of the memory arrangement.
 43. The layer arrangementaccording to one of claim 24, wherein the substrate is one of a siliconwafer or a silicon chip.
 44. The layer arrangement according to one ofclaim 24, further comprising an insulation layer comprising a thirdelectrically insulating material is arranged on at least part of thesurface of the substrate located between the substrate and at least partof the first and/or second layer sequences.
 45. The layer arrangementaccording to one of claim 24, wherein the first layer sequence furthercomprises a first part-layer comprising a first electrically insulatingmaterial and a second part-layer comprising a fourth electricallyinsulating material.
 46. The layer arrangement according to one of claim24, wherein the second layer sequence further comprises a charge-storagepart-layer, a second part-layer comprising a fifth, electricallyinsulating material, a third part-layer comprising a second,electrically conductive material and a fourth part-layer comprising asixth, electrically insulating material.
 47. A memory arrangement havingthe layer arrangement according to one of claim 24, wherein: the atleast one first layer sequence on the first surface region of thesubstrate forms at least part of the logic region of the memoryarrangement; and the at least one second layer sequence on the secondsurface region of the substrate forms at least part of the memory cellregion of the memory arrangement.
 48. The layer arrangement according toone of claim 25, further comprising an insulation layer comprising athird electrically insulating material is arranged on at least part ofthe surface of the substrate located between the substrate and at leastpart of the first and/or second layer sequences.
 49. The layerarrangement according to one of claim 25, wherein the first layersequence further comprises a first part-layer comprising a firstelectrically insulating material and a second part-layer comprising afourth electrically insulating material.
 50. The layer arrangementaccording to one of claim 25, wherein the second layer sequence furthercomprises a charge-storage part-layer, a second part-layer comprising afifth, electrically insulating material, a third part-layer comprising asecond, electrically conductive material and a fourth part-layercomprising a sixth, electrically insulating material.
 51. A memoryarrangement having the layer arrangement according to one of claim 25,wherein: the at least one first layer sequence on the first surfaceregion of the substrate forms at least part of the logic region of thememory arrangement; and the at least one second layer sequence on thesecond surface region of the substrate forms at least part of the memorycell region of the memory arrangement.
 52. The layer arrangementaccording to one of claim 26, wherein the first layer sequence furthercomprises a first part-layer comprising a first electrically insulatingmaterial and a second part-layer comprising a fourth electricallyinsulating material.
 53. The layer arrangement according to one of claim26, wherein the second layer sequence further comprises a charge-storagepart-layer, a second part-layer comprising a fifth, electricallyinsulating material, a third part-layer comprising a second,electrically conductive material and a fourth part-layer comprising asixth, electrically insulating material.
 54. A memory arrangement havingthe layer arrangement according to one of claim 26, wherein: the atleast one first layer sequence on the first surface region of thesubstrate forms at least part of the logic region of the memoryarrangement; and the at least one second layer sequence on the secondsurface region of the substrate forms at least part of the memory cellregion of the memory arrangement.
 55. The layer arrangement according toone of claim 27, wherein the second layer sequence further comprises acharge-storage part-layer, a second part-layer comprising a fifth,electrically insulating material, a third part-layer comprising asecond, electrically conductive material and a fourth part-layercomprising a sixth, electrically insulating material.
 56. A memoryarrangement having the layer arrangement according to one of claim 27,wherein: the at least one first layer sequence on the first surfaceregion of the substrate forms at least part of the logic region of thememory arrangement; and the at least one second layer sequence on thesecond surface region of the substrate forms at least part of the memorycell region of the memory arrangement.
 57. The layer arrangementaccording to claim 28, in which the charge-storage part-layer is one of:a layer comprising polycrystalline silicon with a silicondioxide-silicon nitride-silicon dioxide layer sequence (ONO layer) ascovering layer; or a silicon dioxide-silicon nitride-silicon dioxidelayer sequence (ONO layer).
 58. The layer arrangement according to claim28, wherein the first and/or second electrically conductive materialcomprises polycrystalline silicon.
 59. The layer arrangement accordingto one of claim 28, wherein each of the first, second, third, fourth,fifth and sixth electrically insulating materials, comprises one of:silicon dioxide; silicon nitride; or a silicon dioxide-siliconnitride-silicon dioxide layer sequence (ONO layer).
 60. The layerarrangement according to claim 57, wherein the first and/or secondelectrically conductive material comprises polycrystalline silicon. 61.The layer arrangement according to one of claim 57, wherein each of thefirst, second, third, fourth, fifth and sixth electrically insulatingmaterials, comprises one of: silicon dioxide; silicon nitride; or asilicon dioxide-silicon nitride-silicon dioxide layer sequence (ONOlayer).
 62. The layer arrangement according to one of claim 58, whereineach of the first, second, third, fourth, fifth and sixth electricallyinsulating materials, comprises one of: silicon dioxide; siliconnitride; or a silicon dioxide-silicon nitride-silicon dioxide layersequence (ONO layer).